Embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices including vertical transistors and methods of fabricating the same.
As mobile systems become more supplied and digital home appliances become excessively scaled down, semiconductor devices constituting the mobile systems or the digital home appliances have been more highly integrated. Particularly, various attempts to increase integration density of semiconductor memory devices have been made to store more data in a limited planar area. The semiconductor memory devices may include dynamic random access memory (DRAM) devices which are widely used and employed in the mobile systems and/or the digital home appliances. In general, each of memory cells of the DRAM devices includes a planar cell transistor and a cell capacitor stacked on the planar cell transistor, and the planar cell transistor has a source region and a drain region which are located at the same horizontal level on or in a semiconductor substrate. If a gate width (e.g., a channel length) of the planar cell transistor is reduced to have about 40 nanometers or less, the planar cell transistor may suffer from a short channel effect causing a channel leakage current and the channel leakage current may result in high power consumption.
Recently, vertical transistors have been proposed to overcome the disadvantages of the planar cell transistors. Each of the vertical transistors may include a drain region, a channel region and a source region which are vertically stacked in a semiconductor substrate such as a silicon substrate. Further, each of the vertical transistors may include a gate electrode disposed to cover at least a portion of a sidewall of the channel region. A method of fabricating a vertical transistor is taught in U.S. patent publication No. 2012-0135573 A1 to Kim, entitled “method for manufacturing vertical transistor having one side contact”. If the vertical transistors are employed in the semiconductor memory devices, the integration density of the semiconductor memory devices may be increased without degradation of performance of the semiconductor memory devices.